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參數(shù)資料
| 型號： | ICS843101AG-312LFT |
| 英文描述： | FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| 中文描述： | FEMTOCLOCKS⑩晶體到的LVPECL 312.5MHZ頻率裕合成器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 184K |
| 代理商： | ICS843101AG-312LFT |
843101AG-312
www.icst.com/products/hiperclocks.html
OCTOBER 18, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843101-312
F
EMTO
C
LOCKS
C
RYSTAL
-
TO
-LVPECL
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
ADVANCE INFORMATION
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
V
CC
- 2V
50
Ω
50
Ω
RTT
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
outputs are designed to drive 50
Ω
transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 4A and 4B
show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω
resistor can be tied from the CLK input to
ground.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
P
INS
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω
resistor can be used.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS843101AG-312T | FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AGI-312 | FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AGI-312LF | FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AGI-312LFT | FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AGI-312T | FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843101AG-312T | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AGI-100LF | 功能描述:IC SYNTHESIZER 100MHZ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| ICS843101AGI-100LFT | 功能描述:IC SYNTHESIZER 100MHZ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS843101AGI-312 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AGI-312LF | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
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