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參數(shù)資料
| 型號(hào)： | ICS8430I-71B |
| 英文描述： | 700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| 中文描述： | 700MHz的，低抖動(dòng)，晶體界面/的LVCMOS至3.3的LVPECL頻率合成器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 168K |
| 代理商： | ICS8430I-71B |
8430BYI-71
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 17, 2006
9
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
V
CC
- 2V
50
Ω
50
Ω
RTT
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50
Ω
transmission lines. Matched impedance tech-
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
niques should be used to maximize operating frequency
and minimize signal distortion. There are a few simple ter-
mination schemes.
Figures 4A and 4B
show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recom-
mended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component
process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
TEST_CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω
resistor can be tied from the TEST_CLK to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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|---|---|
| ICS8431-01 | 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER |
| ICS8431-11 | 255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER |
| ICS8431-21 | 350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8431AM-21 | 350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8431AM-21LF | 350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
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