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參數(shù)資料
| 型號： | ICS8430AY-62LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVPECL 32-LQFP |
| 標準包裝： | 250 |
| 系列： | HiPerClockS™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 8430AY-62LF |
ICS8430-62 Datasheet
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ICS8430AY-62 REVISION A JULY 2, 2009
16
2009 Integrated Device Technology, Inc.
The following component footprints are used in this layout example.
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors C14 and C15, as close as possible
to the power pins. If space allows, placement of the decoupling
capacitor on the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin caused by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground) and
the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If VCCA shares the same power supply with VCC, insert the RC filter
R7, C11, and C16 in between. Place this RC filter as close to the
VCCA pin as possible.
Clock Traces and Termination
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system failure.
In the synchronous high-speed digital system, the clock signal is less
tolerable to poor signal quality than other signals. Any ringing on the
rising or falling edge or excessive ring back can cause system failure.
The trace shape and the trace delay might be restricted by the
available space on the board and the component location. While
routing the traces, the clock signal traces should be routed first and
should be locked prior to routing other signal traces.
The traces with 50
transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run adjacent to
each other. Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on the
transmission lines.
Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
Keep the clock trace on the same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace can
affect the trace characteristic impedance and hence degrade
signal quality.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace and
the other signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in this
example.
Crystal
The crystal X1 should be located as close as possible to the pins 24
(XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
Figure 7B. PCB Board Layout for ICS8430-62
R7
X1
R4
TL1, TL21N are 50 Ohm
traces and equal length
C16
C2
PIN 1
C11
C1
TL1
U1
C14
R3
TL1
C15
R2
VIA
Close to the input
pins of the
receiver
R1
TL1N
GND
TL1N
VCCA
VCC
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICS8430AY-62LFT | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8430AYI-61 | 制造商:ICS 制造商全稱:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS8430AYI-61LF | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| ICS8430AYI-61LFT | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:* 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8430AYI-61T | 制造商:ICS 制造商全稱:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
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