500MHZ, C
參數(shù)資料
型號(hào)： ICS8430AY-61LF
廠(chǎng)商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 12/21頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZR DUAL LVPECL 32LQFP
標(biāo)準(zhǔn)包裝： 250
系列： HiPerClockS™
類(lèi)型： 頻率合成器
PLL： 帶旁路
輸入： 晶體
輸出： LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 1249 (CN2011-ZH PDF)
其它名稱(chēng)： 800-1137
8430AY-61LF
8430AY-61
www.idt.com
REV. D JULY 27, 2010
2
ICS8430-61
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 250
≤ M ≤ 500. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N2
nP_LOAD
S_LOAD
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-61 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 500MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (ei-
ther too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430-61 support two
input modes and to program the M divider and N output di-
vider. The two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hard-wired to set the M divider and N output divider to a
T1
T0
TEST Output
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
CMOS Fout
16
M
fVCO =
fxtal x
N
fout =
fVCO
=
16
M
fxtal x
N
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