FEMTOCLOCK
參數(shù)資料
型號(hào): ICS843051AGLFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 17/17頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GENERATOR LVPECL 8TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類(lèi)型: 時(shí)鐘/頻率合成器,時(shí)鐘發(fā)生器
PLL:
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 161.13MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 帶卷 (TR)
其它名稱(chēng): 843051AGLFT
ICS843051AG REVISION A OCTOBER 13, 2010
9
2010 Integrated Device Technology, Inc.
ICS843051 Data Sheet
FEMTOCLOCK CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100
. This can also be
accomplished by removing R1 and making R2 50
. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
R2
100
R1
100
RS
43
Ro ~ 7 Ohm
Driv er_LVCMOS
Zo = 50 Ohm
C1
0.1uF
3.3V
Cry stal Input Interf ace
XTAL_IN
XTAL_OUT
Cry stal Input Interf ace
XTAL_IN
XTAL_OUT
R3
50
C1
0.1uF
R2
50
R1
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
VCC=3.3V
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