IDT / ICS 3.3V LVPECL CLOCK GENERATOR
參數資料
型號: ICS843001AGLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數: 2/16頁
文件大?。?/td> 0K
描述: IC CLOCK GENERATOR 8-TSSOP
標準包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL:
輸入: 晶體
輸出: LVPECL
電路數: 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 226.66MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -30°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 8-TSSOP
包裝: 帶卷 (TR)
其它名稱: 843001AGLFT
IDT / ICS 3.3V LVPECL CLOCK GENERATOR
10
ICS843001AG REV B March 2, 2009
ICS843001
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 93mA = 322.2mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 322.2mW + 30mW = 352.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.352W * 90.5°C/W = 116.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE
θθθθθ
JA
FOR
8-PIN TSSOP, FORCED CONVECTION
θθθθθ
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
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