參數(shù)資料
型號(hào)： ICS8430-61
英文描述： 500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
中文描述： 500MHz的，水晶到3.3V的差分LVPECL頻率合成器
文件頁(yè)數(shù)： 2/15頁(yè)
文件大?。?/td> 175K
代理商： ICS8430-61
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8430-61
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 250
≤
M
≤
500. The frequency
out is defined as follows:
fout =fVCO=fxtalxN
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N2
nP_LOAD
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-61 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 500MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (ei-
ther too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430-61 support two
input modes and to program the M divider and N output di-
vider. The two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hard-wired to set the M divider and N output divider to a
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
M
fVCO =16
N
M
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ICS8430AYI-61 500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
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參數(shù)描述
ICS8430-62 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:500MHz, Crystal-to-3.3V, 2.5V Differential LVPECL Frequency Synthesizer
ICS843071AGI 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO- LVPECL CLOCK GENERATOR
ICS843071AGILF 功能描述:IC CLOCK GENERATOR LVPECL 8TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
ICS843071AGILFT 功能描述:IC CLOCK GENERATOR LVPECL 8TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
ICS843071AGIT 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO- LVPECL CLOCK GENERATOR
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