參數(shù)資料
型號: ICS840004AGLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/7頁
文件大小: 0K
描述: IC FREQ SYNTHESIZER 20-TSSOP
標準包裝: 74
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無/無
頻率 - 最大: 226.66MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 管件
其它名稱: 840004AGLF
3
PS8538D
10/27/09
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PI90LV14/PI90LVT14
1:5 Clock Distribution
Notes:
1. Within-Device skew is defined for identical transitions on similar paths through a device.
2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.
3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV
input swings.
4. The range in which the high level of the input swing must fall while meeting the VPP spec.
5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of the output at
any given temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage, and
temperature.
6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same
direction. This parameter is guaranteed by design and characterization.
7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).
Output Criteria: 60%/40% duty cycle, VOL(max) 0-4V, VOH(min) 2.7V, Load - 7pF (stray plus probes).
8. CL includes probe and fixture capacitance.
9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50 ohms, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest
propagation delay & minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)(8,9).
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