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參數(shù)資料
型號: ICS83940DYLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 2:18 32-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: HiPerClockS™
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:18
差分 - 輸入:輸出: 是/無
輸入: CML,LVCMOS,LVPECL,LVTTL,SSTL
輸出: LVCMOS,LVTTL
頻率 - 最大: 250MHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
其它名稱: 800-1117
83940DYLF
83940DY
www.idt.com
REV. B AUGUST 9, 2010
10
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
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