參數(shù)資料
型號(hào): ICS83115BRT
英文描述: LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
中文描述: 低偏移,1至16的LVCMOS / LVTTL扇出緩沖器
文件頁數(shù): 5/9頁
文件大?。?/td> 180K
代理商: ICS83115BRT
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
5
Integrated
Circuit
Systems, Inc.
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter, RMS
@ 155.52MHz (12KHz to 20MHz)
= 0.09ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
S
H
O
Z
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