參數(shù)資料
型號: ICS8308AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 2:8 24-TSSOP
標準包裝: 2,500
系列: HiPerClockS™
類型: 扇出緩沖器(分配),多路復用器
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/無
輸入: HCSL,LVCMOS,LVDS,LVHSTL,LVPECL,LVTTL,SSTL
輸出: LVCMOS,LVTTL
頻率 - 最大: 350MHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 8308AGILFT
ICS8308AGI REVISION C APRIL 4, 2013
11
2013 Integrated DeviceTechnology, Inc.
ICS8308I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
FIGURE 2C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both differential signals must meet
the V
PP and VCMR input requirements. Figures 2A to 2E show interface
examples for the CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
FIGURE 2A. CLK/nCLK INPUT DRIVEN BY
IDT’S LVHSTL DRIVER
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example in
Figure
2A, the input termination applies for IDT LVHSTL drivers. If you
are using an LVHSTL driver from another vendor, use their
termination recommendation.
FIGURE 2E. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
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