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參數(shù)資料
| 型號： | ICS8305 |
| 英文描述： | LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER |
| 中文描述： | 低偏移，1至4，復用差分/ LVCMOS-TO-LVCMOS/LVTTL扇出緩沖器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 213K |
| 代理商： | ICS8305 |
Integrated
Circuit
Systems, Inc.
8305AG
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 26, 2004
11
ICS8305
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
Input
CLK
nCLK
3.3V
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
and V
must meet the
V
and V
input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A,the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
3E. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
HiPerClockS
Input
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
C2
LVPECL
C1
Zo = 50 Ohm
R1
3.3V
LVDS_Driver
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
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