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參數(shù)資料
| 型號： | ICS680G-01T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 66.6666 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封裝： | 0.173 INCH, TSSOP-24 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 201K |
| 代理商： | ICS680G-01T |
ICS680-01
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER
ZDB AND SYNTHESIZER
IDT / ICS NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 6
ICS680-01
REV F 020305
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70
° C
Note 1: Measured with a 15 pF load.
Note 2: Duty cycle is configuration dependent. Most configurations are min 45% / max 55%.
Note 3: Skew is measured at 1.4 V on rising edges with a 33 MHz ICLK.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
fIN
X1
25
MHz
ICLK
33
MHz
Output Frequency
fOUT
Q0 to Q3, QFB, Note 1
33
MHz
Output Rise Time
tOR
20% to 80%, Note 1
1.5
ns
Output Fall Time
tOF
80% to 20%, Note 1
1.5
ns
Output Clock Duty Cycle
tD
at VDD/2, Note 2
40
60
%
Power-up Time
PLL lock-time from
power-up to 1% of final
frequency
10
ms
PDTS goes high until
stable CLK outputs at
1% of final frequency
2ms
One Sigma Clock Period Jitter
Configuration
dependent
50
ps
Maximum Absolute Jitter
tja
Deviation from mean.
Configuration
dependent.
±200
ps
QFB to ICLK Skew
tPD
Measured at VDD/2,
Note 3
-350
350
Pin-to-pin Skew
QFB, Q0 to Q3, Note 3
-250
250
ps
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