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參數(shù)資料
| 型號(hào)： | ICS680G-01LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER/ZD BUFFER 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 類型： | 時(shí)鐘/頻率合成器，零延遲緩沖器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 2 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 66.67MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.13 V ~ 3.46 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 680G-01LF |
ICS680-01
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER
ZDB AND SYNTHESIZER
IDT / ICS NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 3
ICS680-01
REV H 051310
External Components
The ICS680-01 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD (pins 5 and 16) and GND (pins 6 and 15), as
close to these pins as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50
trace (a commonly used trace
impedance) place a 33
resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20
.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation crystal caps (pF) =
(CL-6)x2
In the equation, CL is the crystal load capacitance. So for a
crystal with a 16 pF load capacitance, two 20 pF[(16-6)x2]
capacitors should be used
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33
series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS680-01. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
18
VDD
Power
Connect to voltage supply.
19
ICLK
Input
Zero Delay Buffer Input. Weak Internal pull-up.
20
25M
Output
25 MHz reference output clock. Weak internal pull-down when tri-state.
21
S1
Input
Select pin 1. See table above.
22
PDTS
Power
Power-down tri-state. Powers down entire chip and tri-states outputs
when low. Internal pull-up resistor.
23
VDD
Power
Connect to voltage supply.
24
X2
XO
Crystal output. Connect this pin to a crystal. Float for clock input.
Pin
Number
Name
Pin
Type
Pin Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS680G-01LFT | 功能描述:IC SYNTHESIZER/ZD BUFFER 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS680G-01T | 功能描述:IC SYNTHESIZER/ZD BUFFER 24TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS68-1 | 制造商:Thomas & Betts 功能描述:Cable Accessories Compression Splice Aluminum Orange |
| ICS69-1 | 制造商:Thomas & Betts 功能描述:SEALEEVE |
| ICS6953BI147 | 制造商:ICS 制造商全稱:ICS 功能描述:DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER |
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