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參數(shù)資料
| 型號： | ICS664G-04LF |
| 英文描述： | PECL Digital Video Clock Source |
| 中文描述： | PECL的數(shù)字視頻時鐘源 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 97K |
| 代理商： | ICS664G-04LF |
ICS664-04
MDS 664-04 A
1
Revision 040805
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
PECL Digital Video Clock Source
Description
The ICS664-04 provides clock generation and
conversion for clock rates commonly needed in HDTV
digital video equipment. The ICS664-04 uses the latest
Phase-Locked Loop (PLL) technology to provide
excellent phase noise and long-term jitter performance
for superior synchronization and S/N ratio.
For audio sampling clocks generated from 27 MHz, use
the ICS661.
Please contact ICS if you have a requirement for an
input and output frequency not included in this
document. ICS can rapidly modify this product to meet
special requirements.
Features
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Clock or crystal input
Low phase noise
Low jitter
Exact (0 ppm) multiplication ratios
Power-down control
Improved phase noise over ICS660
Differential outputs
Block Diagram
PLL Clock
Synthesis
SELIN
Crystal
Oscillator
X2
X1/REFIN
VDD (P2)
VDD (P10)
CLK
CLK
GND (P6)
GND (P5)
S3:0
4
VDD (P3)
VDDO
GND (P12)
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