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參數(shù)資料
| 型號(hào)： | ICS651-03 |
| 英文描述： | VOIP Clock Source |
| 中文描述： | 時(shí)鐘源的VOIP |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 116K |
| 代理商： | ICS651-03 |
VOIP Clock Source
MDS 651-03 A
3
Revision 112603
Integrated Circuit Systems
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS651-03
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS651-03 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01μF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01μF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) Place the 33
series termination resistor (if needed)
close to the clock output to minimize EMI.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS651-03. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS651G-03 | VOIP Clock Source |
| ICS651G-03T | VOIP Clock Source |
| ICS651 | LOW SKEW 1 TO 4 CLOCK BUFFER |
| ICS661 | Precision Audio Clock Source |
| ICS661GI | Precision Audio Clock Source |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS651B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER |
| ICS651BMLF | 功能描述:IC CLK BUFFER 1:4 200MHZ 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:ClockBlocks™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS651BMLFT | 功能描述:IC CLK BUFFER 1:4 200MHZ 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:ClockBlocks™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS651G-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VOIP Clock Source |
| ICS651G-03T | 制造商:ICS 制造商全稱:ICS 功能描述:VOIP Clock Source |
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