
ICS650-44
SPREAD SPECTRUM CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
IDT / ICS SPREAD SPECTRUM CLOCK SYNTHESIZER
7
ICS650-44
REV E 051310
Timing Diagrams
Figure 1: Test and Measurement Setup
Figure 3: Rise and Fall Time Definitions
Figure 5: PDTS to Stable Clock Output Timing
Figure 2: Duty Cycle Definitions
Figure 4: Power Up and PLL Lock Timing
Figure 6: Short Term Jitter Definition
DUT
0.01F
C
LOAD
VDDs
GND
Outputs
VDDO
t
3
Clock
Output
t
4
0V
80% of VDDO
20% of VDDO
1.25 V
PD TS
CLK
Outputs
VO H
t
EN
0 V
t
DIS
1%
1.25 V
VD D O
t
2
Clo c k
t
1
0V
50% o f V D D O
4 ms
10 ms
VDD
0V
VDD
0V
0 ms
Power Up
Tim e
VCO Ram p
Time
PLL Locked
Absolute jitter
(p - p)
Mean value
tJA