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參數(shù)資料
| 型號(hào)： | ICS650-14B |
| 英文描述： | Networking System Clock |
| 中文描述： | 網(wǎng)絡(luò)系統(tǒng)時(shí)鐘 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 45K |
| 代理商： | ICS650-14B |
ICS650-14B
Networking System Clock
MDS 650-14B A
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408)295-9800tel www.icst.com
3
Revision 082800
Printed 11/15/00
PRELIMINARY INFORMATION
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH, SEL pins only
Input Low Voltage, VIL, SEL pins only
Input High Voltage, VIH, OE pin only
Input Low Voltage, VIL, OE pin only
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Frequency error
Absolute Jitter, short term
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
7
V
V
°C
°C
°C
°C
-0.5
0
-40
VDD+0.5
70
85
260
150
Industrial "I" version
Max of 20 seconds
-65
3
5.5
V
V
V
V
V
V
V
V
V
V
Clock Input
Clock Input
VDD/2 + 1
VDD/2 - 1
VDD - 0.5
0.5
2.0
0.8
IOH=-12mA
IOL=12mA
IOH=-8mA
No Load
Each output
2.4
0.4
VDD-0.4
TBD
±50
mA
mA
25.000
MH z
ns
ns
%
ppm
ps
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
All clocks
Variation from mean
1.5
1.5
55
0
45
50
TBD
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CMOS level input, nominal trip point is VDD/2 for 3.3 V or 5 V operation.
External Components
The ICS650R-14B requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01μF should be connected between each VDD and GND on Pins 4 and 6, and Pins 16 and
14, as close to the ICS650R-14B as possible. A series termination resistor of 33
may be used for each
clock output. The 25.00 MHz crystal must be connected as close to the chip as possible. The crystal should
be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these
capacitors is given by the following equation, where C
L
is the crystal load capacitance: Crystal caps (pF) =
(C
L
-6) x 2. So for a crystal with 16 pF load capacitance, two 20 pF caps should be used.
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