參數(shù)資料
型號: ICS621MLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW SKEW 1 TO 4 CLOCK BUFFER
中文描述: 621 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 0.150 INCH, GREEN, SOIC-8
文件頁數(shù): 2/10頁
文件大?。?/td> 171K
代理商: ICS621MLFT
ICS621
LOW SKEW 1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
IDT / ICS
LOW SKEW 1 TO 4 CLOCK BUFFER
2
ICS621
REV B 030907
Pin Assignment (8-pin SOIC)
Pin Assignment (8-pin DFN)
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01
μ
F
should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33
series
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS621 is capable of, careful attention must be paid to board layout.
Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they
do not, the output skew will be degraded. For example, using a 30
series termination on one output (with 33
on
the others) will cause at least 15 ps of skew.
1
2
3
4
5
6
7
8
ICLK
Q1
Q2
Q3
Q4
OE
VDD
GND
1
Q3
Q2
GND
VDD
Q1
Q4
ICLK
OE
5
8
4
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
Input
Clock Input. 3.3 V tolerant input.
2
Q1
Output
Clock Output 1.
3
Q2
Output
Clock Output 2.
4
Q3
Output
Clock Output 3.
5
Q4
Output
Clock Output 4.
6
GND
Power
Connect to ground.
7
VDD
Power
Connect to +1.2 V or +1.8 V.
8
OE
Input
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
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