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參數(shù)資料
| 型號： | ICS581G-02LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK MUX GLITCH FREE 16-TSSOP |
| 產(chǎn)品培訓模塊： | Clock Distibution and Generation 1.0 |
| 標準包裝： | 96 |
| 系列： | ClockBlocks™ |
| 類型： | 扇出緩沖器（分配），零延遲緩沖 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 581G-02LF |
ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ZDB AND MULTIPLEXER
IDT / ICS ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
4
ICS581-01/02
REV L 051310
PLL will run in an open loop.
The ICS581-02 is identical to the ICS581-01 except for the
switching of the input mux. On the ICS581-02, the switching
is automatically controlled by a transition detector. The
transition detector monitors the clock on INA. If this clock
stops, the output of the detector, NO_INA goes high, which
then selects clock input INB to the mux. The definition of the
clock stopping is determined by a timeout selected by input
DIV. If DIV is low, NO_INA will go high after no transitions
have occurred on INA for nominally three cycles of the clock
on INB. If DIV is high, the timeout is nominally 48 cycles of
INB. When INA restarts, the mux immediately switches back
to the INA selection with no timeout.
Input Clock Frequency
The ICS581-01 and ICS581-02 are designed to switch
between two clocks of the same frequency. They will also
operate with different frequencies on each of the two input
clocks. If the two input frequencies require different input
ranges (see table on page two), then the highest range
should be permanently selected. When the selected input
clock is outside this range, jitter and input skew
specifications may not be met. Consult IDT for more
information.
Application Example
A typical application for the ICS581-02 is to provide a backup clock for a system. The backup reliable clock would
be connected to INB while the main clock would be connected to INA. If the main clock failed, the ICS581-02 would
automatically be switched to the backup clock. The following example shows the connection for this.
In this example, the clocks are 155 MHz and so the frequency range is address 11. Both S0 and S1 are left
unconnected, causing the on-chip pull-ups to produce the required high inputs. The same is true for OE0, OE1, and
DIV. In this example, CLK4 is used as the feedback. Note that the feedback path is before the series resistor.
CLK3
S0
CLK4
S1
GND
VDD
OE1
INA
INB
GND
FBIN
OE0
DIV
VDD
CLK1
CLK2
VDD
0.01 F
33
0.01 F
MAIN
BACKUP
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| ICS581G-02LFT | 功能描述:IC CLK MUX GLITCH FREE 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:ClockBlocks™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS581G-02T | 功能描述:IC CLK MUX GLITCH FREE 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:ClockBlocks™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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| ICS5OSK481TILF | 制造商:ICS 制造商全稱:ICS 功能描述:48 MHz Tiny USB Clock Source |
| ICS5OSK481TILFT | 制造商:ICS 制造商全稱:ICS 功能描述:48 MHz Tiny USB Clock Source |
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