參數(shù)資料
型號: ICS580M-01IT
英文描述: Glitch-Free Clock Multiplexer
中文描述: 無干擾時鐘復用器
文件頁數(shù): 3/6頁
文件大?。?/td> 61K
代理商: ICS580M-01IT
ICS580-01
Glitch-Free Clock Multiplexer
MDS 580-01 A
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126 (408) 295-9800tel www.icst.com
3
Revision 030300
Printed 11/28/00
Device Operation and Applications
The ICS580-01 consists of a glitch free mux between INA and INB controlled by SELB. The device is
designed to switch between 2 clocks, whether running or not. In the first example, clocks are running on
both INA and INB. When SELB changes, the output clock goes low after 3 cycles of the output clock
(nominally). The output then stays low for 3 cycles of the new input clock (nominally) and then starts with
the new input clock. This is shown in Figure 1.
Figure 1
INA
INB
SELB
CLK1, 2
In the second example, one of the inputs was selected and running but has since stopped (either high or low).
This is indicated by either NO_INA or NO_INB going high depending on whether INA or INB has
stopped. These signals go high following a selectable time-out period after the clock has stopped. The
timeout period is determined by the DIV input pin. The SELB pin is now changed to select the new input
clock which is running. The output clock immediately goes low and stays low for 3 cycles of the new input
clock and then starts with the new input clock. Figure 2 shows an example of this.
Figure 2
INA
INB
SELB
CLK1, 2
NO_INA
Timeout
相關(guān)PDF資料
PDF描述
ICS580M-01T Glitch-Free Clock Multiplexer
ICS580-01 Glitch-Free Clock Multiplexer
ICS581-01 Zero-Delay Glitch-Free Clock Multiplexer
ICS581G-01 Zero-Delay Glitch-Free Clock Multiplexer
ICS581G-01I Zero-Delay Glitch-Free Clock Multiplexer
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