參數(shù)資料
型號(hào): ICS580M-01
元件分類: 時(shí)鐘及定時(shí)
英文描述: 580 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 4/8頁
文件大小: 152K
代理商: ICS580M-01
Glitch-Free Clock Multiplexer
MDS 580-01 E
4
Revision 080305
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS580-01
Application Example
In the third example, the ICS580-01 is configured to automatically switch clocks when an input stops. The
clock that could stop is connected to INA while the backup clock (always running) is connected to INB. The
output NO_INA is connected to SELB. This means that when the clock on INA stops, NO_INA goes high
selecting the clock on INB which is muxed to the output after three cycles. When the clock on INA restarts,
NO_INA immediately goes low, selecting the clock on INA. The output then switches in the manner
described in the first example.
The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB
are unused and are disabled by grounding OE2 and OE4. A 33
series termination resistor is used on the
clock output and two decoupling capacitors of 0.01
F are used. All other inputs are left floating and are
therefore pulled high by the on-chip pull-ups.
Output Enable
Each output has a dedicated output enable pin. If an output is unused, it should be tri-stated by tying the
appropriate output enable pin to ground.
External Components
The ICS580-01 requires two 0.01
F decoupling capacitors, one between VDDI and GND and one between
VDDC and GND. Series termination resistors of 33
can be used on CLK1 and CLK2.
NO_INA
SELB
NO_INB
DIV
GND
VDDI
OE2
INA
INB
GND
OE4
OE3
OE1
VDDC
CLK1
CLK2
VDD
0.01
F
33
0.01
F
Normal Clock
Backup Clock
Output Clock
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