
ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
IDT / ICS MULTIPLIER AND ZERO DELAY BUFFER
2
ICS570
REV K 073007
Pin Assignment
Clock Multiplier Decoding Table
(Multiplies Input clock by amount shown)
0 = connect directly to ground
M = leave unconnected (self-biases to VDD/2)
1 = connect directly to VDD
*Input range with CLK feedback is double that for CLK/2
S1
VDD
GND
CLK
ICLK
S0
FBIN
CLK/2
1
2
3
4
8
7
6
5
S1
VDD
GND
CLK
ICLK
S0
FBIN
CLK/2
1
2
3
4
8
7
6
5
8 pin (150 mil) SOIC
S1 S0
FBIN from
CLK
FBIN from
CLK/2
ICS570B (3.3 V)
ICS570A (5.0 V)
CLK
CLK/2
CLK
CLK/2 ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2*
#1 #6
pin #7
pin #8
pin #7
pin #8
0
Power Down and Tri-State
-
0
M
x3
x1.5
x6
x3
3.75 to 28
2.5 to 25
0
1
x4
x2
x8
x4
2.75 to 19
2.5 to 19
M
0
x8
x4
x16
x8
2.5 to 9.5
M
x6
x3
x12
x6
2.5 to 12.5
M
1
x10
x5
x20
x10
2.5 to 7.5
1
0
x1
/2
x2
x1
11 to 85
5 to 75
1
M
x16
x8
x32
x16
1.5 to 5
1
x2
x1
x4
x2
5.5 to 37.5
2.5 to 37.5