參數(shù)資料
型號: ICS551MT
英文描述: 1 to 4 Clock Buffer
中文描述: 1至4時(shí)鐘緩沖器
文件頁數(shù): 2/4頁
文件大小: 56K
代理商: ICS551MT
ICS551
1 to 4 Clock Buffer
MDS 551 B
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800tel(408)295-9818fax
2
Revision 091200
Printed 11/14/00
PRELIMINARY INFORMATION
Pin Assignment
Number
1
2
3
4
5
6
7
8
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Type
CI
O
O
O
O
P
P
I
Description
Clock input. Internal pull-up resistor.
Clock Output 1.
Clock Output 2.
Clock Output 3.
Clock Output 4.
Connect to ground.
Connect to +3.3 V or +5.0 V.
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
Pin Descriptions
Key: CI = clock input, I = input, O = output, P = power supply connection
1
8
2
3
4
7
6
5
ICLK
Q2
OE
Q1
Q4
8 pin SOIC
Q3
VDD
GND
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 μF should be connected between VDD on pin 7 and GND on pin 6, and a 33
terminating resistor
may be used on each clock output if the trace is longer than 1 inch.
相關(guān)PDF資料
PDF描述
ICS55201-01 Oscillator, Multiplier, and Buffer with 8 Outputs
ICS552G-02 LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER
ICS552G-02T LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER
ICS552G-03 LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
ICS552G-03T LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
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