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參數(shù)資料
| 型號： | ICS548G-05T |
| 英文描述： | PRELIMINARY INFORMATION MP3 Audio Clock |
| 中文描述： | 初步信息MP3音頻時鐘 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 67K |
| 代理商： | ICS548G-05T |
ICS548-05A
MP3 Audio Clock
MDS 548-05 AC
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
3
Revision 032900
PRELIMINARY INFORMATION
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Core Operating Voltage, VDD
Input High Voltage, VIH, X1/ICLK pin
Input Low Voltage, VIL, X1/ICLK pin
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Power Down Supply Current, IDDPD
Short Circuit Current
Input Capacitance
Frequency synthesis error
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Crystal or Clock Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Start-up Time
Maximum Absolute Jitter, short term
One sigma jitter
Note:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
7
V
V
°C
°C
°C
-0.5
0
VDD+0.5
70
260
150
Max of 10 seconds
-65
2.7
5.5
V
V
V
V
V
V
V
V
Clock input only
Clock input only
(VDD/2)+1
VDD/2
VDD/2
(VDD/2)-1
2
0.8
IOH=-12mA
IOL=12mA
IOH=-4mA
No Load
No Load
CLK output
S0, S1, S2, S3, PDCLK
All selections
2.4
0.4
VDD-0.4
4
5
mA
μA
mA
pF
ppm
±50
7
0
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
VDD=3V to CLK stable
3.6864
MHz
ns
ns
%
ms
ps
ps
2
2
60
10
40
50
±250
70
Electrical Specifications
External Components/ Application Information
The ICS548-05 requires a minimum number of external components for proper operation. A decoupling
capacitor of 0.01μF should be connected between VDD and GND on pins 3 and 5, as close to the
ICS548-05 as possible. Other VDDs can be connected to pin 3. A series termination resistor of 33
may
be used for each clock output. If REFOUT is not used, then REFEN should be connected to ground. The
input crystal must be connected as close to the chip as possible. The input crystal should be fundamental
mode, parallel resonant. For exact accuracy of the output frequencies, the crystal can be tuned with two
identical capacitors to ground, as shown on the block diagram. The value of these two crystal caps should be
equal to (C
L
-6)*2, where C
L
is the crystal load (or correlation) capacitance.
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