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參數(shù)資料
| 型號(hào)： | ICS525RI12LFT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 50 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.150 INCH, LEAD FREE, MO-153, SSOP-28 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 178K |
| 代理商： | ICS525RI12LFT |
ICS525-01/02/11/12
MDS 525-01/02/11/12 R
1
Revision 042506
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
User Configurable Clock
Description
The ICS525-01/02/11/12 are the most flexible way to
generate a high-quality, high-accuracy, high-frequency
clock output from an inexpensive crystal or clock input.
The user can configure the device to produce nearly
any output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked together.
For similar capability with a serial interface, use the
ICS307. For simple multipliers to produce common
frequencies, refer to the ICS50x family of parts, which
are smaller and more cost effective.
These products are intended for clock generation. They
have low output jitter (variation in the output period), but
input to output skew and jitter are not defined nor
guaranteed. For applications which require defined
input to output timing, use the ICS527-01.
Features
Packaged as 28-pin SSOP (150 mil body)
Industrial and commercial versions available in Pb
(lead) free package
User determines the output frequency by setting all
internal dividers
Eliminates need for custom oscillators
No software needed
Online calculator determines register settings
Pull-ups on all select inputs
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Very low jitter
Duty cycle of 45/55 up to 200 MHz
Operating voltage of 3.0 V or 5.5 V
Ideal for oscillator replacement
Industrial temperature version available
For Zero Delay, refer to the ICS527
Block Diagram
VDD
GND
2
CLK
REF
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Divider
Output
Divider
9
73
R6:R0
V8:V0
S2:S0
X1/ICLK
X2
Crystal or clock
input
Optional crystal capacitors
Crystal
Oscillator
PD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS525-01RLF | 160 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-02LF | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS527R-01IT | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-01LFT | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-01LFT | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS525RI-12T | 制造商:ICS 制造商全稱:ICS 功能描述:User Configurable Clock |
| ICS527-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer⑩ User Configurable Zero Delay Buffer |
| ICS527-02 | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer User Configurable PECL Input Zero Delay Buffer |
| ICS527-03 | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer User Configurable PECL Output Zero Delay Buffer |
| ICS527-04 | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer User Configurable PECL input Zero Delay Buffer |
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