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參數(shù)資料
| 型號(hào)： | ICS501BMILFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK MULTIPLIER 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | LOCO™ |
| 類型： | 時(shí)鐘乘法器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 15MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 3.14 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
ICS9WDV3501B
IDTTM/ICSTM Voltage Monitor/Watchdog Timer Circuit
1468—05/30/08
VOLTAGE MONITOR/WATCHDOG TIMER CIRCUIT
1
DATASHEET
Advance Information
General Description:
The 9WDV3501 contains 5 voltage monitoring (VMON)
comparators and a watchdog timer circuit. The external voltage
monitor inputs have a reset threshold of approximately 1.0V.
Various power supplies can easily be monitored with these
inputs by use of a simple resistor ladder to divide the supply rail
down to 1.0V.
There are two RESET# outputs. RESET0# is typically
connected to a microprocessor, while RESET1# is typically
connected to peripheral components.
If any of the VMON inputs drops outside the desired operating
range, both RESET# outputs will be asserted simultaneously.
They will stay low as long as VMON is below the threshold.
After VMON rises above the threshold, RESET0# will begin its
timeout count down and return high after the count down
expires. The count down period depends on the value on the
RST0_DLY(1:0) pins. The minimum value is 50ms and the
maximum value is 300ms. When RESET0# is de-asserted, the
RESET1# output will continue to be asserted for an additional
count down period.
Functional Block Diagram
Features:
5 Precision Voltage Monitors:
Watchdog Timer
Selectable Watchdog and Reset Timing
Two Active Low reset outputs
Precision Timebase with external trim resistor
L
ogi
c
WatchDog
Timer
Reset Timer 0
50 to 300 ms
nominal
Reset Timer 1
50 to 300 ms
nominal
RESET0#
RESET1#
WTB(1:0)
Watchdog
Edge Detector
WDI
1.00V
Bandgap
+
-
+
-
+
-
+
-
+
-
VMON4
VMON0
VMON1
VMON2
VMON3
RST1_DLY(1:0)
RST0_DLY(1:0)
Osc
RP
Master clock
The RESET1# count down period is set by the RST1_DLY(1:0)
inputs. The
additional delay can range from 50ms to 300ms.
This additional reset is designed to hold the peripheral circuits
in reset after the microprocessor has been released from reset.
The VMON circuitry can continue to operate until VDD drops
below 2.3V.
The watchdog timer monitors transitions on the WDI input. This
input is usually driven by a GPIO line from a microprocessor and
is used to detect when the CPU has entered an infinite loop. If a
transition on the WDI input is not detected within the watchdog
time out period, both RESET# outputs will be asserted and will
be as described in the previous paragraph. The watchdog timer
is restarted when RESET1# goes inactive. The watchdog time
out period is selectable using the WTB(1:0) inputs. The
watchdog can be disabled by pulling the WDI_EN pin low.
The 9WDV3501 incorporates a precision RC oscillator that
utilized an external trimming resistor for maximum accuracy.
The recommend value for this resistor is 30K
.
The 9WDV3501 is available in both commercial and industrial
temperature ranges. It is available in a 20-pin QFN or a 20-pin
TSSOP package.
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| ICS501BMT | 功能描述:IC PLL CLK MULTIPLIER 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:LOCO™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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