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參數(shù)資料
| 型號(hào)： | ICS307M-02T |
| 英文描述： | ER 5C 5#8 PIN RECP |
| 中文描述： | 串行可編程時(shí)鐘源 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | ICS307M-02T |
ICS307
Serially Programmable Clock Source
MDS 307 D
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
4
Revision 042501
Setting the Device Characteristics
The tables below show the settings which can be configured, in addition to the VCO and Reference dividers.
CLK1
Maximum
Output
Frequency
Divide
5 V or 3.3 V
10
2
8
4
5
7
3
6
Max. Freq.
Industrial
Version
36
180
45
90
72
50
120
60
S2
S1
S0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
40
200
50
100
80
55
135
67
Table 1. Output Divide and
Maximum Output Frequency
Table 2. CLK2 Output
TTL
0
1
Duty cycle measured at
1.4V
VDD/2
Recommended VDD
5 V
3.3 V
Table 3. Output Duty Cycle Configuration
C1
0
0
1
1
C0
0
1
0
1
VDD = 5 V
22.3 - 0.083 f
23.1 - 0.093 f
23.7 - 0.106 f
24.4 - 0.120 f
VDD = 3.3 V
22.1 - 0.094 f
22.9 - 0.108 f
23.5 - 0.120 f
24.2 - 0.135 f
Table 4. Crystal Load Capacitance
Note: f is the crystal frequency, between 10 and
27 MHz. Effective load capacitance will be higher
for crystal frequencies lower than 10 MHz. If a
clock input is used, set C1 = 0 and C0 = 0.
Note: The TTL bit optimizes the duty cycle at
different VDD. When VDD is 5 V, set to 0
for a near-50% duty cycle with TTL levels.
When VDD is 3.3 V, set this bit to a 1, so the
50% duty cycle is achieved at VDD/2.
F1
0
0
1
1
F0
0
1
0
1
CLK2
REF
REF/2
OFF (Low)
CLK1/2
0 = Connect directy to ground
1 = Connect directly to VDD
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