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    參數(shù)資料
    型號: ICS251PMT
    廠商: IDT, Integrated Device Technology Inc
    文件頁數(shù): 1/10頁
    文件大?。?/td> 0K
    描述: IC CLK SYNTHESIZER FP SGL 8-SOIC
    標準包裝: 2,500
    系列: VersaClock™
    類型: 時鐘/頻率合成器,擴展頻譜時鐘發(fā)生器
    PLL:
    輸入: 時鐘,晶體
    輸出: CMOS
    電路數(shù): 1
    比率 - 輸入:輸出: 1:1
    差分 - 輸入:輸出: 無/無
    頻率 - 最大: 200MHz
    除法器/乘法器: 是/無
    電源電壓: 3.15 V ~ 3.45 V
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
    供應商設備封裝: 8-SOIC
    包裝: 帶卷 (TR)
    其它名稱: 251PMT
    DATASHEET
    FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
    ICS251
    IDT FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
    1
    ICS251
    REV D 030212
    Description
    The ICS251 is a low cost, single-output, field programmable
    clock synthesizer. The ICS251 can generate an output
    frequency from 314 kHz to 200 MHz and may employ
    Spread Spectrum techniques to reduce system
    electro-magnetic interference (EMI).
    Using IDT’s VersaClocksoftware to configure the PLL and
    output, the ICS251 contains a One-Time Programmable
    (OTP) ROM to allow field programmability. Programming
    features include 4 selectable configuration registers.
    The device employs Phase-Locked Loop (PLL) techniques
    to run from a standard fundamental mode, inexpensive
    crystal, or clock. It can replace multiple crystals and
    oscillators, saving board space and cost.
    The device also has a power-down feature that tri-states the
    clock outputs and turns off the PLLs when the PDTS pin is
    taken low.
    The ICS251 is also available in factory programmed custom
    versions for high-volume applications.
    Features
    8-pin SOIC package
    Four addressable registers
    Input crystal frequency of 5 to 27 MHz
    Clock input frequency of 3 to 150 MHz
    Output clock frequencies up to 200 MHz
    Configurable Spread Spectrum Modulation
    Operating voltage of 3.3 V
    Replaces multiple crystals and oscillators
    Controllable output drive levels
    Advanced, low-power CMOS process
    Available in RoHS compliant packaging
    Block Diagram
    Crystal
    Oscillator
    PLL Clock Synthesis,
    Spread Spectrum and
    Control Circuitry
    CLK
    PDTS (output and PLL)
    OTP ROM
    with PLL
    Divider
    Values
    S1:0
    2
    VDD
    GND
    X2
    Crystal or
    clock input
    External capacitors are
    required with a crystal input.
    X1/ICLK
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