A – Analog P – Power I – Input O – Output 2008 2008B ICS2008
參數(shù)資料
型號: ICS2008BY-10LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/22頁
文件大?。?/td> 0K
描述: IC TIME CODE RCVR/GEN 44-TQFP
標(biāo)準(zhǔn)包裝: 160
類型: SMPTE 時間代碼接收器,發(fā)生器
應(yīng)用: 多媒體
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 44-TQFP-EP(10x10)
包裝: 管件
產(chǎn)品目錄頁面: 1252 (CN2011-ZH PDF)
其它名稱: 2008BY-10LF
800-1026
3
ICS2008B
ICS2008B
Pin Descriptions
TYPE:
A – Analog P – Power I – Input O – Output 2008 2008B ICS2008
PIN NUMBER
PIN
NAME
TYPE
DE SC RIP T I O N
TQFP
PLCC
12, 10
18, 16
Y1, Y2
AI
Video inputs from camera or other source. NOTE: This is also the Y
(Luma) input for S-VHS and HI-8 systems.
11, 9
17, 15
C1, C2
AI
C (Chroma) inputs for S-VHS and HI-8 systems. In NTSC systems, this
pin should be tied to its respective Y input.
15
21
DTHRESH
AI
Data Threshold bypass input.
13
19
STHRESH
AI
SYNC Threshold bypass input.
14
20
CTHRESH
AI
Clamp Threshold bypass input.
8
14
Y OUT
AO
Video output. This is also the Y (Luma) output in S-Video mode.
7
13
C OUT
AO
C (Chroma) output for S-VHS and HI-8 systems.
41
3
FRAME
AI
Color Frame A/B input. This input is self biased (See Applications).
42
4
CLICK
AI
LTC SYNC input. This input is self biased (See Applications).
44
6
LTCIN+
AI
SMPTE LTC input+. This input is self biased (See Applications).
43
5
LTCIN–
AI
SMPTE LTC input–. This input is self biased (See Applications).
1
7
LTCOUT
AO
SMPTE LTC output
20
26
LRCLK
O
SMPTE LTC receive clock output.
22
28
VITCOUT
O
SMPTE VITC output to video mixer circuit.
21
27
VITCGATE
O
VITC gate indicates VITC code is being output for video overlay.
18
24
TxD
O
UART Transmit data
16
22
RxD
I
UART Receive data
17
23
CTS*
I
Clear to Send
19
25
RTS*
O
Ready to Send
4
10
XTAL1
I
14.318 MHz crystal input.
3
9
XTAL2
O
14.318 MHz crystal oscillator output.
2
8
LFC
AI
Tie to +5 VDC
24, 23
30, 29
A1-A0
I
Address bus
27
33
IOR*
I
Read Enable (active low)
30
36
IOW*
I
Write Enable (active low)
25
31
SMPTECS*
I
SMPTE port chip select (active low)
26
32
UARTCS*
I
UART chip select (active low)
40
2
RESET
I
Master reset (active high)
38–31
44–37
D7-D0
I/O
Bi-directional data bus
39
1
INTR
O
Interrupt Request (active high)
5
11
AVDD
P
Analog VDD
6
12
AVSS
P
Analog Ground
29
35
VDD
P
Digital VDD
28
34
VSS
P
Digital
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