- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄10615 > ICS2008BVLF (IDT, Integrated Device Technology Inc)IC TIME CODE RCVR/GEN 44-PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS2008BVLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 4/22頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TIME CODE RCVR/GEN 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類(lèi)型： | SMPTE 時(shí)間代碼接收器，發(fā)生器 |
| 應(yīng)用： | 多媒體 |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 2008BVLF 800-2355-5 ICS2008BVLF-ND |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)
ICS2008B
12
ICS2008B
UART Registers
The UART emulates a 6850. Since the UART is tailored to
MIDI applications, some of the generic 6850 functions have
been omitted. The registers described below reflect that.
The two UART registers, Command/Status and Data, are
accessible to the processor as shown in the following map.
UART Command/Status Register
Bit Rate — This field selects the bit rate for data transmit and
receive. After a master reset, its value is 11. One of the three
bit rates must be selected in order to start the UART’s
operation. Writing a 11 will reset the UART.
TC1, TC0 — Bits 6 and 5, Transmit Control, provide control
for transmit interrupt (when TBE is true), RTS control, and
transmit BREAK level.
RIE — Bit 7, Receive interrupt enable, when set to one,
enables the UART to interrupt the processor when the receive
buffer is full or a receive overrun has occurred.
RBF — Bit 0, Receive Buffer Full, is set to 1 when read data
is available in the UART data register. It is cleared to 0 when
the UART data register is read.
TBE — Bit 1, Transmit Buffer Empty, is cleared to 0 when
data is written to the UART data register. It is set to 1 when the
UART transfers that data to its output shift register.
CTS — Bit 3, Clear-to-Send, is an active low status bit
indicating the state of the CTS* input pin. A 0 in this bit
position indicates that the modem or receiving device is ready
to receive characters. A 1 indicates not ready. When CTS is
inactive, 1, TBE is held at 0, the not-empty state.
FE — Bit 4, Framing Error, when set to 1, indicates that the
receive character was improperly framed by the start and stop
bits. It is detected by the absence of the first stop bit. This
indicator is valid as long as the character data is valid.
OV — Bit 5, Receiver Overrun, is an error flag indicating that
one or more characters in the data stream has been lost. It is set
to 1 when a new character overwrites an old character which
has not been read. The overrun error is cleared to 0 when a
character is read from the UART data register.
IRQ — Bit 7, Interrupt Request, is a status bit which reflects
the state of the interrupt request from the UART to the
processor. When IRQ is 1, an interrupt is pending. Otherwise,
no interrupt is pending.
The UART data register is actually two registers, a transmit
buffer and a receive buffer. Writing to the data register causes
the transmit buffer to be written. Reading from the data regis-
ter causes the receive buffer to be read.
UARTCS* A1 A0
REGISTER
0
X
0
UART Command/Status Register
0X
1
UART Data Register
UART Command Register
Bit Rate
(00 - 9600, 10 - 38.4K)
(01 - 31.25K, 11 - Reset)
Reserved
TC1, TC0 Transmit Control
00 - RTS* – low, Tx IRQ disabled
01 - RTS* – low, Tx IRQ enabled
10 - RTS* – high, Tx IRQ disabled
11 - RTS* – low, Transmit BREAK,
Tx IRQ disabled
RIE - Receive Interrupt Enable
UART0 (write)
7
6
5
4
3
2
1
0
UART2 Status Register
RBF – Receive Buffer Full (1-Full)
TBE – Transmit Buffer Empty (1-Empty)
Reserved
CTS – Clear-to-Send (0-Active)
FE
– Framing Error (1-Error)
OV – Receiver Overrun (1-Overrun)
Reserved
IRQ – Interrupt Request (1-Active)
UART0 (read)
UART Data Register
UART1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-J0W-MY-F3 | CONVERTER MOD DC/DC 5.5V 50W |
| MAX203CWP+G36 | IC TXRX RS232 5V W/CAPS 20-SOIC |
| VE-J0W-MY-F2 | CONVERTER MOD DC/DC 5.5V 50W |
| ICS664G-03LF | IC CLK SOURCE DGTL VIDEO 16TSSOP |
| MAX203CPP+G36 | IC TXRX RS232 5V W/CAPS 20-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS2008BVLFT | 功能描述:IC TIME CODE RCVR/GEN 44-PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話(huà)，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064 |
| ICS2008BVT | 功能描述:IC TIME CODE RCVR/GEN 44-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話(huà)，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064 |
| ICS2008BY-10 | 功能描述:IC TIME CODE RCVR/GEN 44-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話(huà)，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064 |
| ICS2008BY-10LF | 功能描述:IC TIME CODE RCVR/GEN 44-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類(lèi)型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤(pán) 包裝:帶卷 (TR) 其它名稱(chēng):296-32523-2TPS65198RUYT-ND |
| ICS2008BY-10LFT | 功能描述:IC TIME CODE RCVR/GEN 44-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話(huà)，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。