參數(shù)資料
型號： ICS1893BKLFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 121/133頁
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 56-VQFN
標(biāo)準(zhǔn)包裝： 1,000
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 56-VFQFP-EP（8x8）
包裝： 帶卷 (TR)
其它名稱： 1893BKLFT
ICS1893BF, Rev. F, 5/13/10
May, 2010
88
Chapter 7 Management Register Set
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.14.1 Node Configuration (bit 19.15)
The Node Configuration bit indicates the NOD/MODE.
In Node mode:
– The SQE Test default setting is enabled.
– The Carrier Sense signal (CRS) is asserted in response to either transmit or receive activity.
The ICS1893BF will only operate in the Node Configuration.
7.14.2 Hardware/Software Priority Status (bit 19.14)
The Hardware/Software Priority Status bit indicates the SW mode.
The (MDIO) register bits control the ICS1893BF configuration.
The ICS1893BF will only operate in the Software Configuration.
7.14.3 Remote Fault (bit 19.13)
The ISO/IEC specification defines bit 5.13 as the Remote Fault bit, and bit 19.13 is functionally identical to
bit 5.13. The Remote Fault bit is set based on the Link Control Word received from the remote link partner.
When this bit is a logic:
Zero, it indicates the remote link partner does not detect a Link Fault.
One, it indicates to an STA that the remote link partner detects a Link Fault.
7.14.4 ICS Reserved (bits 19.12:10)
See Section 7.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.
7.14.5 Auto-MDI/MDIX (bits 19. 9:8) (New)
The ICS1893BF includes the Auto-MDI/MDIX crossover feature. The Auto-MDI/MDIX feature automatically
selects the correct MDI or MDIX configuration to match the cable plant by automatically swapping transmit
and receive signal pairs at the PHY. Auto-MDI/MDIX is defaulted on but may be disabled for test purposes
using either the AMDIX_EN (pin 10) or by writing (bits 19. 9:8). See Table 7-22 for AMDIX_EN (19,9) and
MDI_MODE (19,8) operation.
When AMDIX_EN (bit 19,9) is set to 0, the twisted pair transmit/receive is forced by the MDI_MODE bit
(19,8).
Note: Holding (Pin 10) AMDIX_EN low will also disable the Auto_MDIX function and force pins TP_AP
and TP_AN to be the transmit pair and TP_BP and TP_BN to be the receive pair. AMDIX_EN has
a built in 50K Ohm internal pull-up.
Table 7-22. AMDIX_EN (Pin 10) and Control Bits 19. 9:8
AMDIX_EN
(Pin 10)
AMDIX_EN
[Reg 19:9]
MDI_MODE
[Reg 19:8]
Tx/Rx MDI
Configuration
x0
0
straight
x0
1
cross
01
x
straight
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