參數(shù)資料
型號： ICS1893BKILF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 84/133頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 56-VQFN
標準包裝： 260
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 56-VFQFP-EP（8x8）
包裝： 管件
其它名稱： 1893BKILF
800-2354-5
ICS1893BKILF-ND
ICS1893BF, Rev. F, 5/13/10
May, 2010
54
Chapter 7 Management Register Set
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.2.2 Loopback Enable (bit 0.14)
This bit controls the Loopback mode for the ICS1893BF. Setting this bit to logic:
Zero disables the Loopback mode.
One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver,
and the collision detection circuitry. (The STA can override the ICS1893BF from disabling the collision
detection circuitry in Loopback mode by writing logic one to bit 0.7.) When the ICS1893BF is in Loopback
mode, the data presented at the MAC transmit interface is internally looped back to the MAC receive
interface. The delay from the assertion of Transmit Data Enable (TXEN) to the assertion of Receive Data
valid (RXDV) is less than 512 bit times.
7.2.3 Data Rate Select (bit 0.13)
This bit provides a means of controlling the ICS1893BF data rate. Its operation depends on the state of
several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12).
When the ICS1893BF is configured for:
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893BF isolates this bit 0.13 and uses the
10/100SEL input pin to establish the data rate for the ICS1893BF. In this Hardware mode:
– Bit 0.13 is undefined.
– The ICS1893BF provides a Data Rate Status bit (in the QuickPoll Detailed Status Register, bit 17.15),
which always shows the setting of an active link.
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.13 depends on the
Auto-Negotiation Enable bit 0.12. When the Auto-Negotiation sublayer is:
– Enabled, the ICS1893BF isolates bit 0.13 and relies on the results of the auto-negotiation process to
establish the data rate.
– Disabled, bit 0.13 determines the data rate. In this case, setting bit 0.13 to logic:
Zero selects 10-Mbps ICS1893BF operations.
One selects 100-Mbps ICS1893BF operations.
7.2.4 Auto-Negotiation Enable (bit 0.12)
This bit provides a means of controlling the ICS1893BF Auto-Negotiation sublayer. Its operation depends
on the HW/SW input pin.
When the ICS1893BF is configured for:
Hardware mode, (that is, the HW/SW pin is logic zero), the ICS1893BF isolates bit 0.12 and uses the
ANSEL (Auto-Negotiation Select) input pin to determine whether to enable the Auto-Negotiation
sublayer.
Note: In Hardware mode, bit 0.12 is undefined.
Software mode, (that is, the HW/SW pin is logic one), bit 0.12 determines whether to enable the
Auto-Negotiation sublayer. When bit 0.12 is logic:
– Zero:
The ICS1893BF disables the Auto-Negotiation sublayer.
The ICS1893BF bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data
rate and the duplex mode.
– One:
The ICS1893BF enables the Auto-Negotiation sublayer.
The ICS1893BF isolates bit 0.13 and bit 0.8.
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ICS1893BKLF 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BKLFT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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