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參數(shù)資料
| 型號： | ICS1893AFLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 99/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標準包裝： | 1,000 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1893AFLFT |
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Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
65
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.3.6
IEEE Reserved Bits (bits 1.10:7)
The IEEE reserves these bits for future use. When an STA:
Reads a reserved bit, the ICS1893AF returns a logic zero.
Writes a reserved bit, the STA must use the default value specified in this data sheet.
Both the ISO/IEC standard and the ICS1893AF reserve the use of some Management Register bits. ICS
uses some reserved bits to invoke ICS1893AF test functions. To ensure proper operation of the
ICS1893AF, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA
write the default value to all reserved bits during all Management Register write operations.
Reserved bits 1.10:7 are Command Override Write (CW) bits. When bit 16.15, the Command Register
Override bit, is logic:
Zero, the ICS1893AF prevents all STA writes to CW bits.
One, an STA can modify the value of these bits.
8.3.7
MF Preamble Suppression (bit 1.6)
Status Register bit 1.6 is the Management Frame (MF) Preamble Suppression bit. The ICS1893AF sets bit
1.6 to inform the STA of its ability to receive frames that do not have a preamble. When this bit is logic:
Zero, the ICS1893AF is indicating it cannot accept frames with a suppressed preamble.
One, the ICS1893AF is indicating it can accept frames that do not have a preamble.
Although the ICS1893AF supports Management Frame Preamble Suppression, its default value for bit 1.6
is logic zero. This default value ensures that bit 1.6 is backward compatible with the ICS1890, which does
not have this capability. As the means of enabling this feature, the ICS1893AF implements bit 1.6 as a
Command Override Write bit, instead of as a Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to
enable MF Preamble Suppression in the ICS1893AF. [See the description of bit 16.15, the Command
Override Write Enable bit, in Section 8.11, “Register 16: Extended Control Register”.]
8.3.8
Auto-Negotiation Complete (bit 1.5)
An STA reads bit 1.5 to determine the state of the ICS1893AF auto-negotiation process. The ICS1893AF
sets the value of this bit using two criteria. When its Auto-Negotiation sublayer is:
Disabled, the ICS1893AF sets bit 1.5 to logic zero.
Enabled, the ICS1893AF sets bit 1.5 to a value based on the state of the Auto-Negotiation State
Machine. In this case, it sets bit 1.5 to logic one only upon completion of the auto-negotiation process.
This setting indicates to the STA that a link is arbitrated and the contents of Management Registers 4, 5,
and 6 are valid. For details on the auto-negotiation process, see Section 7.2, “Functional Block:
Bit 1.5 is a latching high (LH) bit. (For more information on latching high and latching low bits, see Section
Note:
An Auto-Negotiation Restart does not clear an LH bit. However, performing two consecutive reads
of this register provides the present state of the bit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGLF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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