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| 型號(hào)： | ICS1892Y |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 111/148頁(yè) |
| 文件大小： | 816K |
| 代理商： | ICS1892Y |
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Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1892, Rev. D, 2/26/01
February 26, 2001
111
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
RXDV
36
Output
Receive Data Valid.
The ICS1892 asserts RXDV to indicate to the MAC/repeater that data is
available on the MII Receive Bus (RXD[3:0]). The ICS1892:
Asserts RXDV after it detects and recovers the Start-of-Stream
delimiter, /J/K/. (For the timing reference, see
Chapter 10.5.6, “MII /
100M Stream Interface: Synchronous Receive Timing”
.)
De-asserts RXDV after it detects either the End-of-Stream delimiter
(/T/R/) or a signal error.
Note:
RXDV is synchronous with the Receive Data Clock, RXCLK.
RXER
38
Output
Receive Error.
In 100Base-TX mode, the ICS1892 asserts a signal on the RXER pin
under two conditions:
When errors are detected during the reception of valid frames.
When a False Carrier is detected.
Note:
1. The ICS1892 asserts a signal on RXER upon detection of a False
Carrier so that repeater applications can prevent the propagation of a
False Carrier.
2. RXER always transitions synchronously with RXCLK.
RXTRI
39
Input
Receive (Interface), Tri-State.
The input on this pin is from a MAC. When the signal on this pin is logic:
Low, the MAC indicates that it is not in a tri-state condition.
High, the MAC indicates that it is in a tri-state condition. In this case,
the ICS1892 acts to ensure that only one PHY is active at a time.
PHY address 00 will also act as RXTRI.
Transmit Clock.
The ICS1892 generates this clock signal to synchronize the transfer of
data from the MAC/Repeater Interface to the ICS1892. When the mode is:
10Base-T, the TXCLK frequency is 2.5 MHz.
100Base-TX, the TXCLK frequency is 25 MHz.
Transmit Data 0–3.
TXD0 is the least-significant bit and TXD3 is the most-significant bit of
the MII transmit data nibble received from the MAC/repeater.
While the ICS1892 asserts TXEN, the signals on the TXD0–TXD3 pins
are sampled by the ICS1892 synchronously on the rising edges of
TXCLK.
TXCLK
43
TXD0,
TXD1,
TXD2,
TXD3
45,
46,
47,
48
Input
Table 9-6.
MAC/Repeater Interface Pins: Media Independent Interface (MII) (
Continued
)
Pin
Name
Pin
Number
Pin
Type
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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