- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360742 > ICS1523M High-Performance Programmable Line-Locked Clock Generator PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS1523M |
| 英文描述： | High-Performance Programmable Line-Locked Clock Generator |
| 中文描述： | 高性能可編程線鎖定時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 1216K |
| 代理商： | ICS1523M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
19
ICS1523
Use a PC board with at least four layers: one power, one
ground, and two signal.
No special cutouts are required for power and ground
planes.
All supply voltages must be supplied from a common
source and must ramp up together.
Flux and other board surface debris can degrade the perfor-
mance of the external loop filter. Ensure that the 1523 area of
the board is free of contaminants.
Specific Layout Guidelines
1. Digital Supply (VDD)
Bypass pin 1 (VDD) to pin 2
(VSS) with 4.7-μF and 0.1-μF capacitors, located as close
as possible to the pins. Traces must be maximally wide and
include multiple surface-etched vias to the appropriate
plane.
2. External Loop Filter
The use of an external loop fil-
ter is strongly recommended in All Designs.
Locate loop
filter components as close to pins 8 and 9 (EXTFIL and
EXTFILRET) as possible
.
Typical loop filter values are
6.8K
W
for the series resistor, 3300 pF RF-type capacitor for
the series capacitor, and 33 pF for the shunt capacitor. (For
details, see the
Frequently Asked Questions
part of the
ICS1523 Applications Guide
, FAQ2 and FAQ3.).
3. Analog PLL Supply (VDDA)
Decouple pin 10
(VDDA) with a series ferrite bead. Bypass the supply end
of the bead with 4.7-μF and 0.1-μF capacitors. Bypass pin
10 to pin 11 (VSSA) with a 0.1-μF capacitor. Locate these
components as close as possible to the pins. Traces must
be maximally wide and have multiple surface-etched vias to
the power or ground planes.
.
4. PECL Current Set Resistor
Locate PECL current-
set resistor as close as possible to pin 24 (IREF). Bypass
pin 24 to ground with a 0.1 μF capacitor.
General Layout Guidelines
5. PECL Outputs
Implement these outputs as
microstrip transmission lines. The trace widths shown are
for 75
W
characteristic impedance, presuming .067 in.
between layers. Locate the optional series snubbing re-
sistors as close as possible to the pins. If the termination
resistors are included on-board, locate them as close as
possible to the load and connect directly to the power and
ground planes.
[These termination resistors are omitted if the load device
implements them internally. For details, see the ICS appli-
cation note on microstrip and striplines (1572AN1) and
within the
ICS1523 Applications Guide
, the application
note on
Designing a Custom Interface for the ICS1523
(1523AN4.)]
6. Output Driver Supply
Bypass pin 18 (VDDQ) to pin
19 (VSSQ) with 4.7-μF and 0.1-μF capacitors, located as
close as possible to the pins. Traces must be maximally
wide and include multiple surface-etched vias to the ap-
propriate plane.
7. SSTL_3 Outputs
SSTL_3 outputs can be used like
conventional CMOS rail-to-rail logic or as a terminated
transmission line system at higher-output frequencies.
With terminated outputs, the considerations of item 5,
PECL Outputs apply. See JEDEC documents JESD8-A
and JESD8-8.
Note: Drawing is not to scale. It is for illustrative purposes only.
4
5
6
7
1
I
1
2
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1524 | Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1524M | Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1524MT | Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1526 | Video Clock Synthesizer |
| ICS1526GLF | Video Clock Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1523MLF | 功能描述:IC SYNTHESIZER VIDEO CLK 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ICS1523MLFT | 功能描述:IC VIDEO CLK SYNTHESIZER 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS1523MT | 功能描述:IC VIDEO CLK SYNTHESIZER 24-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1524 | 制造商:ICS 制造商全稱:ICS 功能描述:Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1524AM | 功能描述:IC CLK GEN SSTL_3/PECL 24-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。