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參數(shù)資料
| 型號： | ICS1522 |
| 英文描述： | User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator |
| 中文描述： | 用戶可編程視頻時鐘發(fā)生器/線鎖定時鐘再生 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 366K |
| 代理商： | ICS1522 |
2
ICS1522
Overview
The
ICS1522
is ideally suited to provide the graphics
system clock signals required by high-performance video
DACs. Fully programmable feedback and reference divider
capability allow virtually any frequency to be generated,
not just simple multiples of the reference frequency. The
ICS1522
uses the latest generation of frequency synthesis
techniques developed by ICS and is completely suitable
for the most demanding video applications.
PLL Synthesizer Description -
Ratiometric Mode
The
ICS1522
generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is
a closed-loop feedback system that drives the output
frequency to be ratiometrically related to the reference
frequency pro-vided to the PLL (see Block Diagram). The
reference frequency is generated by an on-chip crystal
oscillator or the reference frequency may be applied to the
ICS1522
from an external frequency source, typically
horizontal sync from another dis-play system.
The phase-frequency detector shown in the Block Diagram
drives the voltage-controlled oscillator, or VCO, to a
frequency that will cause the two inputs to the phase-
frequency detector to be matched in frequency and phase.
This occurs when:
F(VCO): = F(XTAL1) . Feedback Divider
Reference Divider
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency
provided to the part (assuming correctly programmed
dividers).
The VCO gain is programmable, which permits the
ICS1522
to be optimized for best performance at all operating fre-
quencies.
The feedback divider may be programmed for any modulus
from 64 to 2048 in steps of one followed by a divide by 1,
2, 4 or 8 feedback post-scaler.
The reference divider may be programmed for any modulus
from 1 to 1024 in steps of one.
Output Post-scaler
A programmable post-scaler may be inserted between the
VCO and the CLK+ and CLK- outputs of the
ICS1522
. This
is useful in generating of lower frequencies, as the VCO
has been optimized for high-frequency operation.
The post-scaler allows the selection of dividing the VCO
frequency by either 1, 2, 4 or 8.
Load Clock Divider
The
ICS1522
has an additional programmable divider
(referred to in the Block Diagram as the load counter) that
is used to generate the LOAD clock frequency for the
video DAC. The modulus of this divider may be set to 3, 4,
5, 6, 8, or 10 under register control. The design of this
divider permits the output duty factor to be 50/50, even
when odd modulus is selected. The input frequency to this
divider is the output of the output post-scaler described
above.
Digital Inputs - ICS1522
The programming of the
ICS1522
is performed serially by
using the
SDATA
,
SCLK
, and
SELn
pins to load the 7, 11
bit internal memory locations.
Single bit changes are accomplished by addressing the
appro-priate memory location and writing only 11 bits of
data, not by writing all 77 data bits.
For proper programming of the
ICS1522
, it is important
that all transitions of the
SELn
input occur during the same
state of the
SCLK
input.
SDATA is shifted into a 15 bit serial register on the rising
edge of
SCLK
while
SELn
is low. The first bit loaded is R/
Wn followed by a 3 bit address and 11 bit data (both
address & data are LSB first). When a rising edge of
SCLK
occurs while
SELn
is high (
SDATA
ignored), the contents
of the serial register are loaded into the addressed 11 bit
memory location if R/Wn is low. If R/Wn is high upon the
above condition, the data from the addressed memory
location is loaded into the serial shift register and
SDATA
is set as an output. The 3 bit address and 11 bit data will be
serially shifted out of the
ICS1522
on the
SDATA
pin on
the rising edge of
SCLK
while
SELn
is low (see Timing
Diagram).
An additional control pin on the
ICS1522
,
PDEN
can be
used to disable the phase-frequency detector in line-locked
applica-tions. When disabled, the phase detector will ignore
any inputs and allow the VCO to coast. This feature is
useful in systems using composite sync.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1522M | User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator |
| ICS1523 | High-Performance Programmable Line-Locked Clock Generator |
| ICS1523M | High-Performance Programmable Line-Locked Clock Generator |
| ICS1524 | Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1524M | Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1522M | 制造商:ICS 制造商全稱:ICS 功能描述:User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator |
| ICS1523 | 制造商:ICS 制造商全稱:ICS 功能描述:High-Performance Programmable Line-Locked Clock Generator |
| ICS1523M | 功能描述:IC VIDEO CLK SYNTHESIZER 24-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1523MLF | 功能描述:IC SYNTHESIZER VIDEO CLK 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ICS1523MLFT | 功能描述:IC VIDEO CLK SYNTHESIZER 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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