參數(shù)資料
型號: ICM7555CN
廠商: NXP SEMICONDUCTORS
元件分類: 模擬波形發(fā)生器
英文描述: General purpose CMOS timer
中文描述: PULSE, 0.5 MHz, TIMER, PDIP8
封裝: 0.300 INCH, PLASTIC, MO-001, SC504-8, SOT97-1, DIP-8
文件頁數(shù): 2/9頁
文件大?。?/td> 105K
代理商: ICM7555CN
Philips Semiconductors Linear Products
Product specification
ICM7555
General purpose CMOS timer
August 31, 1994
338
EQUIVALENT BLOCK DIAGRAM
NOTE
:
UNUSED INPUTS SHOULD BE CONNECTED TO APPROPRIATE VOLTAGE FROM TRUTH TABLE.
VDD
8
R
6
5
2
R
1
R
COMPARATOR
A
+
COMPARATOR
B
+
FLIP–FLOP
RESET
4
OUTPUT
3
OUTPUT
DISCHARGE
7
N
1
THRESHOLD
CONTROL
VOLTAGE
TRIGGER
TRUTH TABLE
THRESHOLD VOLTAGE
TRIGGER VOLTAGE
RESET
1
OUTPUT
DISCHARGE SWITCH
DON’T CARE
DON’T CARE
LOW
LOW
ON
>2/3(V+)
> 1/3(V+)
HIGH
LOW
ON
V
TH
< 2/3
DON’T CARE
V
TR
> 1/3
<1/3(V+)
HIGH
STABLE
STABLE
HIGH
HIGH
OFF
NOTES:
1. RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER
RATING
UNITS
V
DD
V
TRIG1
V
CV
V
TH
V
RST
I
OUT
P
DMAX
Supply voltage
+18
V
Trigger input voltage
Control voltage
> -0.3 to
Threshold input voltage
<V
DD
+ 0.3
V
RESET input voltage
Output current
100
mA
Maximum power dissipation, T
A
= 25
°
C (still air)
2
N package
1160
mW
D package
780
mW
°
C
°
C
T
STG
Storage temperature range
-65 to +150
T
SOLD
Lead temperature (Soldering 60s)
300
NOTES:
1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than
V
+ 0.3V or less than GND -0.3V may cause destructive latch-up. For this reason it is recommended that no inputs from external sources
not operating from the same power supply be applied to the device before its power supply is established. In multiple systems, the supply of
the ICM7555 must be turned on first.
2. Derate above 25
°
C, at the following rates:
N package at 9.3mW/
°
C
D package at 6.2mW/
°
C
3. See “Power Dissipation Considerations” section.
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