參數(shù)資料
型號(hào)： ICM200E
廠商： Electronic Theatre Controls, Inc.
英文描述： Megapixel (UXGA) Digital Color CMOS Image Sensor
中文描述： 百萬像素（UXGA）下數(shù)字彩色CMOS圖像傳感器
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 679K
代理商： ICM200E
IC M200E
2 Megapixel (UXGA) Digital Color CMOS Image Sensor
Preliminary Data Sheet V1.1
C opyright 2004, IC Media C orporation
http://www.ic-media.com/
9/22/2004
Page
9
Table 1. Bare Die Pad Assignments
(continued)
Pin
17
Name
SIF_MS
Class
*
D, I
Function
Indicates whether the SIF interface is in master mode
(autoload mode) or in slave mode. When the MSSEL pin is
pulled down during power up, the sensor’s SIF interface is
operated as a SIF slave device waiting to be controlled by
an external SIF master, such as a microprocessor. When the
MSSEL pin is pulled up during power up, the sensor’s SIF
interface is first acting as a SIF master device trying to read
from an external SIF EEPROM. After that, the SIF
interface returns to slave mode.
Selection: 0 = slave and 1= master.
Pixel clock output
Reserved, do not connect
Reserved, do not connect
Output enable: 0: enable, 1: disable
Data output bit 0 determines whether the sensor’s
HYSYNC and VSYNC signals will work under master
mode or slave mode. If pulled up, the sensor will output the
HYSNYC and VSYNC signals to the backend chip, which
is the master mode; if pulled down, the sensor will accept
the HSYNC and VYSNC signals from the backend chip to
control the sensor’s internal frame timing, which is the
slave mode.
Data output bit 1; if pull up or pull down is applied to this
pin, AD_IDL[0] (Sub ID) is 1 or 0 respectively.
Data output bit 2; if pull up or pull down is applied to this
pin, AD_IDL[1] (Sub ID) is 1 or 0 respectively.
Data output bit 3; if pull up or pull down is applied to this
pin, AD_IDL[2] (Sub ID) is 1 or 0 respectively.
Data output bit 4; if pull up or pull down is applied to this
pin, AD_IDL[3] (Sub ID) is 1 or 0 respectively.
Data output bit 5; if pull up or pull down is applied to this
pin, TIMING_CONTROL_LOW[1] (HSYNC polarity) is
1 or 0 respectively.
Data output bit 6; if pull up or pull down is applied to this
pin, the initial value of TIMING_CONTROL_LOW[2]
(VSYNC polarity) is 1 or 0 respectively.
Data output bit 7
Data output bit 8
Data output bit 9
Data output bit 10
SIF data
SIF clock
18
19
20
23
24
PCLK
N/C
N/C
OEN
DOUT[0]
D, O
D, O
D, O
D, I, N
D, I/O
25
DOUT[1]
D, I/O
26
DOUT[2]
D, I/O
27
DOUT[3]
D, I/O
28
DOUT[4]
D, I/O
31
DOUT[5]
D, I/O
32
DOUT[6]
D, I/O
33
34
35
36
37
38
*
Class Codes:
A – analog signal, D – digital signal, I – input, O – output, P – power or ground, U – internal pull-up,
N – internal pull-down, N/C – no connection.
DOUT[7]
DOUT[8]
DOUT[9]
DOUT[10]
SIF_SDA
SIF_SCL
D, O
D, O
D, O
D, O
D, I/O
D, I/O
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