參數(shù)資料
型號(hào)： ICM-108BPA
廠商： Electronic Theatre Controls, Inc.
英文描述： 1.3 million pixel Color CMOS image sensor
中文描述： 130萬(wàn)像素彩色CMOS圖像傳感器
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 449K
代理商： ICM-108BPA
ICM108B 1.3 million pixel CMOS sensor
Data Sheet V 1.1 November, 2002
1. Preliminary Pin Assignment
Pin #
14
2000, 2001, 2002 IC Media Corporation & IC Media Technology Corp.
11/22/2002
page
4
COMPANY CONFIDENTIAL
Name
CLKSEL
Class*
D, I, N
Function
Clock source selection
0: clocks pass PLL, use XIN (pin 12)
1: bypass PLL, use CLKIN (pin 11)
External clock source; bypass PLL
Crystal oscillator in, or external clock in; if external
clocks used, leave Xout (pin 13) unconnected
Crystal oscillator out
Pixel clock output
Output enable. 0: enable, 1: disable
LSB of SIF slave address
SIF master/slave selection. 0: slave, 1: master
SIF clock
SIF data
Power down control, 0: power down, 1: active
Resistor to ground = 25 K
@ 48 MHz main clock,
(or 50K
@ 24 MHz main clock)
Chip reset, active low
Data output bit 10
Data output bit 9
Data output bit 8
Data output bit 7
Data output bit 6; if pulled up/down, the initial value
of TIMING_CONTROL_LOW[2] (VSYNC polarity)
is 1/0
Data output bit 5; if pulled up/down, the initial value
of TIMING_CONTROL_LOW[1] (HSYNC polarity)
is 1/0
Data output bit 4; if pulled up/down, the initial value
of AD_IDL[3] (Sub ID) is 1/0
Data output bit 3; if pulled up/down, the initial value
of AD_IDL[2] (Sub ID) is 1/0
Data output bit 2; if pulled up/down, the initial value
of AD_IDL[1] (Sub ID) is 1/0
Data output bit 1; if pulled up/down, the initial value
of AD_IDL[0] (Sub ID) is 1/0
Data output bit 0; if pulled up/down, the synchron-
ization mode is in master/slave mode which requires
HSYNC and VSYNC operating in output/input mode
Horizontal sync signal
Vertical sync signal
Flash light control
Analog ramp output
Sensor analog power
Sensor analog ground
Sensor digital power
Sensor digital ground
Digital power
Digital ground
11
12
CLKIN
XIN
D, I, N
A, I
13
33
35
31
32
2
1
10
17
XOUT
PCLK
OEN
SIF ID
MSSEL
SCL
SDA
POWERDN
RSET
A, O
D, O
D, I, N
D, I, N
D, I, U
D, I/O
D, I/O
D, I, N
A, I
8
48
47
46
45
44
RSTN
DOUT[10]
DOUT[9]
DOUT[8]
DOUT[7]
DOUT[6]
D, I, U
D, I/O
D, I/O
D, I/O
D, O
D, I/O
43
DOUT[5]
D, I/O
40
DOUT[4]
D, I/O
39
DOUT[3]
D, I/O
38
DOUT[2]
D, I/O
37
DOUT[1]
D, I/O
36
DOUT[0]
D, I/O
3
5
34
15
30,7
29,9
19
18
41,4
42,6
HSYNC
VSYNC
FLASH
RAMP
VDDA
GNDA
VDDD
GNDD
VDDK
GNDK
D, I/O
D, I/O
D, O
A, O
P
P
P
P
P
P
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