
ICM102A C IF CMOS sensor
Data Sheet Version 1.0 July 2002
2000, 2001, 2002 IC Media Corporation & IC Media Technology Corp.
7/24/2002
web site:
http://www.ic -media.c om/
web site:
http://www.ic -media.c om.tw/
page
4
1. Pin Assignment
Pin #
14
Name
CLKSEL
Class*
D, I, N
Function
Clock source selection. 0: internal oscillator, 1:
CLKIN
External clock source
Oscillator in
Oscillator out
Pixel clock output
Output enable. 0: enable, 1: disable
Lsb of SIF slave address
SIF master/ slave selection. 0: slave, 1: master
SIF clock
11
12
13
34
36
32
33
2
CLKIN
XIN
XOUT
PCLK
OEN
SIFID
MSSEL
SCL
D, I, N
A, I
A, O
D, O
D, I, N
D, I, N
D, I, U
D,
I/O
D,
I/O
D, I, N
A, I
D, I, U
D, O
D,
I/O
1
SDA
SIF data
10
16
8
48
47
POWERDN
RSET
RSTN
DOUT[7]
DOUT[6]
Power down control, 0: power down, 1: active
Resistor to ground = 39 K
@ 12 MHz main clock
Chip reset, active low
Data output bit 7
Data output bit 6; if pulled up/ down, the initial
value of TIMING_CONTROL_LOW[2] (VSYNC
polarity) is 1/ 0
Data output bit 5; if pulled up/ down, the initial
value of TIMING_CONTROL_LOW[1] (HSYNC
polarity) is 1/ 0
Data output bit 4; if pulled up/ down, the initial
value of AD_IDL[3] (Sub ID) is 1/ 0
Data output bit 3; if pulled up/ down, the initial
value of AD_IDL[2] (Sub ID) is 1/ 0
Data output bit 2; if pulled up/ down, the initial
value of AD_IDL[1] (Sub ID) is 1/ 0
Data output bit 1; if pulled up/ down, the initial
value of AD_IDL[0] (Sub ID) is 1/ 0
Data output bit 0; if pulled up/ down, the
synchronization mode is in master/ slave mode
which requires HSYNC and VSYNC operating in
output/ input mode
Horizontal sync signal
46
DOUT[5]
D,
I/O
44
DOUT[4]
D,
I/O
D,
I/O
D,
I/O
D,
I/O
D,
I/ O
41
DOUT[3]
39
DOUT[2]
38
DOUT[1]
37
DOUT[0]
3
HSYNC
D,
I/O
D,
I/O
D, O
A, O
P
P
P
P
5
VSYNC
Vertical sync signal
35
15
7, 31
9, 30
19
17
FLASH
RAMP
VDDA
GNDA
VDDD
GNDD
Flash light control
Analog ramp output
Sensor analog power
Sensor analog ground
Sensor digital power
Sensor digital ground