參數(shù)資料
型號: ICL7662CPAZ
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: CMOS Voltage Converter
中文描述: SWITCHED CAPACITOR CONVERTER, 10 kHz SWITCHING FREQ-MAX, PDIP8
封裝: ROHS COMPLIANT, PLASTIC, DIP-8
文件頁數(shù): 9/10頁
文件大?。?/td> 230K
代理商: ICL7662CPAZ
9
Changing the ICL7662 Oscillator Frequency
It may be desirable in some applications, due to noise or other
considerations, to increase the oscillator frequency. This is
achieved by overdriving the oscillator from an external clock, as
shown in Figure 20. In order to prevent possible device latchup,
a 1k
resistor must be used in series with the clock output. In
the situation where the designer has generated the external
clock frequency using TTL logic, the addition of a 10k
pullup
resistor to V+ supply is required. Note that the pump frequency
with external clocking, as with internal clocking, will be 1/2 of
the clock frequency. Output transitions occur on the positive-
going edge of the clock.
It is also possible to increase the conversion efficiency of the
ICL7662 at low load levels by lowering the oscillator frequency.
This reduces the switching losses, and is achieved by
connecting an additional capacitor, COSC, as shown in Figure
21. However, lowering the oscillator frequency will cause an
undesirable increase in the impedance of the pump (C
1
) and
reservoir (C
2
) capacitors; this is overcome by increasing the
values of C
1
and C
2
by the same factor that the frequency has
been reduced. For example, the addition of a 100pF capacitor
between pin 7 (OSC) and V+ will lower the oscillator frequency
to 1kHz from its nominal frequency of 10kHz (a multiple of 10),
and thereby necessitate a corresponding increase in the value
of C
1
and C
2
(from 10mF to 100mF).
Positive Voltage Doubling
The ICL7662 may be employed to achieve positive voltage
doubling using the circuit shown in Figure 22. In this
application, the pump inverter switches of the ICL7662 are
used to charge C
1
to a voltage level of V+ -V
F
(where V+ is
the supply voltage and V
F
is the forward voltage drop of
diode D
1
). On the transfer cycle, the voltage on C
1
plus the
supply voltage (V+) is applied through diode C
2
to capacitor
C
2
. The voltage thus created on C
2
becomes (2V+) (2V
F
) or
twice the supply voltage minus the combined forward
voltage drops of diodes D
1
and D
2
.
The source impedance of the output (V
OUT
) will depend on
the output current, but for V+ = 15V and an output current of
10mA it will be approximately 70
.
FIGURE 19. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
1
2
3
4
8
7
6
5
ICL7662
“1”
V+
1
2
3
4
8
7
6
5
ICL7662
“N”
10
μ
F
+
-
10
μ
F
-
+
V
OUT
-
μ
F
10
μ
F
+
-
1
2
3
4
8
7
6
5
+
-
10
μ
F
ICL7662
V
OUT
V
+
+
-
10
μ
F
V
+
CMOS
GATE
1k
FIGURE 20. EXTERNAL CLOCKING
1
2
3
4
8
7
6
5
+
-
ICL7662
V
OUT
V
+
+
-
C
2
C
1
C
OSC
FIGURE 21. LOWERING OSCILLATOR FREQUENCY
1
2
3
4
8
7
6
5
ICL7662
V+
D
2
C
1
C
2
V
OUT
=
(2V+) - (2V
F
)
+
-
+
-
D
1
NOTE: D
1
and D
2
can be any suitable diode.
FIGURE 22. POSITIVE VOLTAGE DOUBLER
ICL7662
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