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參數(shù)資料
| 型號： | ICL7149 |
| 廠商： | Intersil Corporation |
| 英文描述： | Quad LVDS Receiver with -4 to 5V Common-mode Range 24-TSSOP -40 to 85 |
| 中文描述： | 33 / 4位，自動量程萬用表 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 111K |
| 代理商： | ICL7149 |
3-36
Timing Waveform
Pin Descriptions
FIRST DEINTEGRATE
UNDERRANGE
AUTO ZERO
UNDERRANGE
UNDERRANGE
AUTO ZERO
AUTO ZERO
SECOND AUTO ZERO
FOURTH AUTO ZERO
AUTO ZERO
SECOND INTEGRATE
SECOND DEINTEGRATE
THIRD AUTO ZERO
THIRD INTEGRATE
THIRD DEINTEGRATE
FOURTH INTEGRATE
FOURTH DEINTEGRATE
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FIRST AUTO ZERO
FIRST INTEGRATE
FIGURE 1. LINE FREQUENCY CYCLES (1 CYCLE = 1000 INTERNAL CLOCK PULSES = 2000 OSCILLATION CYCLES)
I/O
PIN NUMBER
DESCRIPTION
O
1
Segment Driver POL/AC
O
2
Backplane 2
O
3
Backplane 1
I
4
V+
I
5
V-
I
6
Reference Input
O
7
Lo
Hi
O
8
I/O
9
Deintegrate
I/O
10
Analog Common
I
11
Int I
I
12
Int V/
I
13
Triple Point
I
14
Auto Zero Capacitor (C
AZ
)
Integrate Capacitor (C
INT
)
Beeper Output
I
15
O
16
I
17
mA/
μ
A
/V/A
Hi
DC/Lo
AC
I
18
I
19
I
20
Hold
O
21
Oscillator Out
I
22
Oscillator In
O
23
Segment DRIVER k/m
O
24
Segment Driver
/A
Segment Driver M
/
μ
A
O
25
O
26
Segment Driver Lo Bat/V
O
27
Segment Driver B
0
/C
0
Segment Driver A
0
/D
0
Segment Driver G
0
/E
0
Segment Driver A
1
/D
1
Segment Driver G
1
/E
1
Segment Driver F
1
/DP
1
Segment Driver B
2
/C
1
Segment Driver B
3
/C
3
Segment Driver ADG
3
/E
3
O
28
O
29
O
32
O
33
O
34
O
35
O
39
O
40
NOTE: For segment drivers, segments are listed as (segment for
backplane 1)/(segment for backplane 2). Example: pin 27; segment
B
0
is on backplane 1, segment C
0
is on backplane 2.
I/O
PIN NUMBER
DESCRIPTION
ICL7139, ICL7149
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|---|---|
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