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參數(shù)資料
| 型號： | ICL7139CPL |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Quad LVDS Receiver with -2 to 4.4V Common-mode Range 16-SOIC -40 to 85 |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP40 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 111K |
| 代理商： | ICL7139CPL |
3-38
Range 1 Deintegrate
At the beginning of the deintegrate cycle, the polarity of the
voltage on the integrator capacitor (C
INT
) is checked, and
either the DElNT+ or DElNT- is asserted. The integrator
capacitor C
INT
is then discharged with a current equal to
V
REF
/R
DElNT
. The comparator monitors the voltage on C
INT
.
When the voltage on C
INT
is reduced to zero (actually to the
V
OS
of the comparator), the comparator output switches, and
the current count is latched. If the C
INT
voltage zero-crossing
does not occur before 4000 counts have elapsed, the over-
load flag is set. “OL” (overload) is then displayed on the LCD. If
the latched result is between 360 and 3999, the count is trans-
ferred to the output latches and is displayed. When the count
is less than 360, an underrange has occurred, and the
ICL7139 and ICL7149 then switch to range 2 - the 40V scale.
Range 2
The range 2 measurement begins with an autozero cycle
similar to the one that preceded range 1 integration. Range 2
cycle length however, is one AC line cycle, minus 360 clock
cycles. When performing the range 2 cycle, the signal is inte-
grated for 100 clock cycles, distributed throughout one line
cycle. This is done to maintain good normal mode rejection.
Range 2 sensitivity is ten times greater than range 1 (100 vs
10 clock cycle integration) and the full scale voltage of
range 2 is 40V. The range 2 deintegrate cycle is identical to
the range 1 deintegrate cycle, with the result being displayed
only for readings greater than 360 counts. If the reading is
below 360 counts, the ICL7139 and ICL7149 again asserts
the internal underrange signal and proceeds to range 3.
Range 3
The range 3V or 4V full scale measurement is identical to the
range 2 measurement, except that the input signal is inte-
grated during the full 1000 clock cycles (one line frequency
cycle). The result is displayed if the reading is greater than
360 counts. Underrange is asserted, and a range 4 measure-
ment is performed if the result is below 360 counts.
Range 4
This measurement is similar to the range 1, 2 and 3 mea-
surements, except that the integration period is 10,000 clock
cycles (10 line cycles) long. The result of this measurement
is transferred to the output latches and displayed even if the
reading is less than 360.
Autozero
After finding the first range for which the reading is above
360 counts, the display is updated and an autozero cycle is
entered. The length of the autozero cycle is variable which
results in a fixed measurement period of 24,000 clock cycles
(24 line cycles).
DC Current
Figure 4 shows a simplified block diagram of the analog
section of the ICL7139 and ICL7149 during DC current
measurement. The DC current measurements are very
similar to DC voltage measurements except: 1) The input
voltage is developed by passing the input current through a
0.1
(HI current ranges), or 9.9
(LOW current ranges)
+
-
+
-
+
-
TRIPLE
POINT
C
AZ
C
INT
R
DEINT
AZ
DEINT-
DEINT-
V
REF
INTEGRATOR
COMPARATOR
TO LOGIC SECTION
6.7V
ANALOG
COMMON
LOW I
R
INTI
INT I
80
μ
A
C
AZ
C
INT
R
DEINT
AZ
AZ
AZ
COMMON
T
T
DEINT+
DEINT+
V+
V-
T = (INT)(AR)(AZ)
AR = AUTORANGE CHOPPER
AZ = AUTOZERO
INT = INTEGRATE
V
REF
9.9
0.1
HIGH I
I
FIGURE 4. DETAILED CIRCUIT DIAGRAM FOR DC CURRENT MEASUREMENT
ICL7139, ICL7149
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