參數(shù)資料
型號: ICE1QS01
廠商: INFINEON TECHNOLOGIES AG
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Controller for Switch Mode Power Supplies Supporting Low Power Standby and Power Factor Correction (PFC)
中文描述: 控制器開關(guān)電源支持低功耗待機(jī)和功率因數(shù)校正(PFC物料供應(yīng))
文件頁數(shù): 11/21頁
文件大小: 484K
代理商: ICE1QS01
ICE1QS01
Version 1.4
11
27
Apr 2004
SRC (Regulation and soft start capacitor)
The feedback capacitor is connected to pin SRC. The feedback voltage V
SRC
has two main func-
tions.
Function I (MOS FET on time): V
SRC
provides the switch off reference voltage. If V
PCS
(which con-
tains the primary current information) exceeds the V
SRC
voltage the external MOS transistor is
switched off.
Function II (MOS FET off time for frequency reduction): At low load the frequency is reduced by
ignoring zero crossing signals after the transformer demagnetization. V
SRC
determines the action of
the 4-bit up-down-counter which contains the number of zero crossings to be ignored. The content
of the up-down-counter is compared with the number of zero-current crossings of V
RZI.
If the
number of zero-current crossings in each period after the transformer demagnetization is equal to
the up-down-counter content the MOS is switched on. At low load conditions when V
SRC
is below
3.5V the counter is increased by one every 50 msec. The result is that the MOS transistor off-time
increases and duty cycle decreases. At high load conditions when V
SRC
is higher than 4.4V the
counter content is reduced by one every 50msec. So MOS transistor off-time will be reduced. With
this off-time regulation switching jitter can be eliminated.
The up-down-counter is immediately set to 0001 if a load jump occurs and V
SRC
exceeds 4.8 V.
This ensures that full power can be provided instantaneously.
The following table shows the SRC voltage range and the corresponding up-down counter action.
The information provided by V
SRC
is stored in two independent flip flops. An internal timer creates a
trigger pulse with a period of 50 msec. Every time the pulse occures the up-down counter checks
the status flip flops and acts depending on the flip flop information. After this pulse the flip flops are
reset. So change of voltage range is noticed by the logic only once during the 50 ms period. In the
diagram below the behaviour of the up-down counter is depicted in more detail.
SRC voltage range
up-down-counter action
1: VSRC< 3.5V
count forward
2: 3.5<VSRC<4.4
stop count
3: VSRC>4.4
count backward
4: VSRC> 4.8
set up-down-counter to1
4.5 V
3.5 V
n
n + 1
n + 1
VSRC
D iagram 1
tim er pulse tp
50 m sec
tp
status of
up-dow n
counter
tp
tp
tp
tp
tp
tp
tp
tp
n
n + 1
n + 1
n + 1
n - 1
n - 2
n - 3
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