參數(shù)資料
型號(hào): IC80C32-12PL
英文描述: CMOS SINGLE CHIP 8-BIT MICROCONTROLLER
中文描述: CMOS單芯片8位微控制器
文件頁(yè)數(shù): 11/48頁(yè)
文件大?。?/td> 274K
代理商: IC80C32-12PL
Integrated Circuit Solution Inc.
MC002-0B
11
IC80C52
IC80C32
The detail description of each bit is as follows:
PSW:
Program Status Word. Bit Addressable.
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
P
Register Description:
CY
PSW.7
AC
PSW.6
F0
PSW.5
Carry flag.
Auxiliary carry flag.
Flag 0 available to the user for
general purpose.
Register bank selector bit 1.
(1)
Register bank selector bit 0.
(1)
Overflow flag.
Usable as a general purpose flag
Parity flag. Set/Clear by hardware each
instruction cycle to indicate an odd/even
number of “1” bits in the accumulator.
RS1
RS0
OV
P
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0
Note:
1. The value presented by RS0 and RS1 selects the corre-
sponding register bank.
RS1
RS0
Register Bank
Address
0
0
1
1
0
1
0
1
0
1
2
3
00H-07H
08H-0FH
10H-17H
18H-1FH
PCON:
Power Control Register. Not Bit Addressable.
7
6
5
4
3
2
1
0
SMOD
GF1
GF0
PD
IDL
Register
SMOD
Description:
Double baud rate bit. If Timer 1 is used to generate
baud rate and SMOD=1, the baud rate is doubled
when the serial port is used in modes 1, 2, or 3.
Not implemented, reserve for future use.
(1)
Not implemented, reserve for future use.
(1)
Not implemented, reserve for future use.
(1)
General purpose flag bit.
General purpose flag bit.
Power-down bit. Setting this bit activates power-
down operatio in the IC80C52/32.
Idle mode bit. Setting this bit activates idle mode.
operation in the IC80C52/32. If 1s are written to
PD and IDL at the same time, PD takes precedence.
GF1
GF0
PD
IDL
Note:
1. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
IE:
Interrupt Enable Register. Bit Addressable.
7
6
5
4
3
2
1
0
EA
ET2
ES
ET1
EX1
ET0 EX0
Register Description:
EA
IE.7
Disable all interrupts. If EA=0, no interrupt
will be acknowledged. If EA=1, each
interrupt source is individually enabled
or disabled by setting or clearing its
enable bit.
Not implemented, reserve for future use.
(5)
IE.6
ET2
IE.5
Enable or disable the Timer 2 overflow
interrupt.
Enable or disable the serial port interrupt.
Enable or disable the Timer 1 overflow
interrupt.
Enable or disable External Interrupt 1.
Enable or disable the Timer 0 overflow
interrupt.
Enable or disable External Interrupt 0.
ES
ET1
IE.4
IE.3
EX1
ET0
IE.2
IE.1
EX0
IE.0
Note:
To use any of the interrupts in the 80C51 Family, the
following three steps must be taken:
1. Set the
EA
(enable all) bit in the IE register to 1.
2. Set the coresponding individual interrupt enable bit in
the IE register to 1.
3. Begin the interrupt service routine at the corresponding
Vector Address of that interrupt (see below).
Interrupt Source
IE0
TF0
IE1
TF1
RI & TI
TF2 and EXF2
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
4. In addition, for external interrupts, pins
INT0
and
INT1
(P3.2 and P3.3) must be set to 1, and depending on
whether the interrupt is to be level or transition activated,
bits IT0 or IT1 in the TCON register may need to be set to
0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5.
User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
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