參數(shù)資料
型號: IC62LV256-100UI
英文描述: 32K x 8 Low Power SRAM with 3.3V
中文描述: 32K的× 8低功耗SRAM與3.3V
文件頁數(shù): 8/9頁
文件大?。?/td> 88K
代理商: IC62LV256-100UI
IC62LV256
8
Integrated Circuit Solution Inc.
ALSR007-0A 10/5/2001
WRITE CYCLE NO. 2 (
CE
Controlled)
(1,2)
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE
t
SA
t
HA
t
PWE
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
D
IN
CE
WE
D
OUT
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
V
IH
.
相關(guān)PDF資料
PDF描述
IC62LV256-100U 32K x 8 Low Power SRAM with 3.3V
IC62LV256-100TI 32K x 8 Low Power SRAM with 3.3V
IC62LV256-100T RES 82.5 OHM 1% 1206 1110-0820
IC62LV256-100N 32K x 8 Low Power SRAM with 3.3V
IC62LV256-100JI 32K x 8 Low Power SRAM with 3.3V
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