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參數(shù)資料
| 型號： | IC61LV256-10T |
| 英文描述： | 32K x 8 Hight Speed SRAM with 3.3V |
| 中文描述： | 32K的× 8 Hight高速SRAM與3.3V |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 122K |
| 代理商： | IC61LV256-10T |
IC61LV256
8
Integrated Circuit Solution Inc.
AHSR027-0B
11/28/2003
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
WRITE CYCLE NO. 2
(
WE
Controlled,
OE
is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(
WE
Controlled,
OE
is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
> V
IH
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC61LV256-10TG | 32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-10TI | 32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-10TIG | 32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-12J | 32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-12JG | 32K x 8 Hight Speed SRAM with 3.3V |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC61LV256-10TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-10TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-10TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-12J | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-12JG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
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