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參數(shù)資料
| 型號(hào)： | IC43R32400-5BG |
| 英文描述： | 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| 中文描述： | 100萬(wàn)× 32位× 4個(gè)銀行（128兆位）DDR SDRAM內(nèi)存 |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 3877K |
| 代理商： | IC43R32400-5BG |
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IC43R32400
Integrated Circuit Solution Inc.
DDR003-0B 11/10/2004
7
Mode Register Set (MRS)
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2, A1, A0)
This field specifies the data length of column access and selects the Burst Length.
Addressing Mode Select Field (A3)
The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and
Interleave Mode support burst length of 2, 4 and 8. Full page burst length is only for Sequential mode.
CAS# Latency Field (A6, A5, A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first read
data. The minimum whole value of CAS# Latency depends on the frequency of CK. The minimum whole
value satisfying the following formula must be programmed into this field.
tCAC(min) _ CAS# Latency X tCK
Test Mode field :A7; DLL Reset Mode field : A8
These two bits must be programmed to “00” in normal operation.
( BA0, BA1)
Mode Resistor Bitmap
X 1 0 2, 3, 0, 1
X 1 1 3, 0, 1, 2
0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
2, 3, 0, 1
3, 2, 1, 0
Burst Length Start Address
A2
2
X
X
X
4
X
Sequential
Interleave
A1 A0
X
X
0
0
0
1
0
1
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
8
Brst Definition, Addressing Sequence of Sequential and Interleave Mode
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