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參數(shù)資料
| 型號(hào)： | IC42S32400-6BG |
| 英文描述： | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| 中文描述： | 100萬(wàn)× 32位× 4個(gè)銀行（128兆）內(nèi)存 |
| 文件頁(yè)數(shù)： | 12/62頁(yè) |
| 文件大?。?/td> | 899K |
| 代理商： | IC42S32400-6BG |
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IC42S32400
IC42S32400L
12
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005
CLK
COMMAND
DIN B2
NOP
WRITEA
WRITEB
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN B0
DIN B1
DQ’s
DIN B3
1 Clk Interval
T0
T2
T1
T3
T4
T5
T6
T7
T8
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
WRITEA
NOP
NOP
NOP
NOP
NOP
READ B
NOP
DIN A0
don’t care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN A0
don’t care
don’t care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
CAS# latency=2
tCK2, DQ’s
CAS# latency=3
tCK3, DQ’s
CLK
WRITE
COMMAND
BANK (S)
ROW
NOP
NOP
Precharge
NOP
NOP
Activate
BANK
COL n
DIN
n
n + 1
DQM
ADDRESS
DQ
tWR
tRP
: dont care
T0
T2
T1
T3
T4
T5
T6
Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3)
The Read command that interrupts a write burst without auto precharge function should be issued one cycle after
the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must
be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the
following figure).Once the Read command is registered,the data inputs will be ignored and writes will not be
executed.
Write Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
should be issued
m
cycles after the clock edge in which the last data-in element is registered,where
m
equals tWR/
tCK rounded up to the next whole number.In addition,the DQM signals must be used to mask input data,starting
with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/
PrechargeAll command is entered (refer to the following figure).
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC42S32400-6BI | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-6BIG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-6T | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-6TG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-6TI | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S32400-6BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-6BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-6T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-6TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-6TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
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